How does cache coherency protocol work?
In a modern multi-core processor, every core has its own private "local" cache (L1 and L2) to store frequently used data. The problem arises when Core A and Core B both load the same piece of data from the main memory. If Core A changes that value, Core B is now working with "stale" or incorrect data.
A Cache Coherency Protocol is the set of rules that ensures every core in a system sees the most up-to-date version of data, maintaining a single, consistent view of memory across the entire CPU.
The most common way CPUs stay in sync is through a process called Bus Snooping.
Imagine a group chat where everyone is working on a shared document. Whenever someone makes a change, they shout it out to the group. In a CPU, all the caches are connected to a common bus. Each cache controller "snoops" (monitors) the bus transactions to see if another core is requesting or modifying a memory address that it currently holds in its own local cache.
The most widely used coherency protocol is MESI. Every line of data in your cache is marked with one of four states:
M (Modified): This core has the only valid copy of the data, and it has changed it (it’s "dirty"). The version in the main RAM is now outdated.
E (Exclusive): This core has the only copy of the data, but it matches the main RAM. No other core has it.
S (Shared): Multiple cores have a copy of this data. It matches the main RAM. It is safe to read but not to write.
I (Invalid): The data in this cache is "junk" or out of date. If the core needs it, it must fetch it again.
The real magic of the protocol happens when a core wants to change data:
The Request: Core A wants to write to a memory address that is currently in the Shared (S) state in both Core A and Core B.
The Invalidation: Core A sends an "Invalidate" signal across the bus.
The Snoop: Core B's cache controller sees the signal, realizes it has that address, and marks its local copy as Invalid (I).
The Upgrade: Core A now has the only valid copy. It changes the data and marks its state as Modified (M).
The Result: If Core B tries to read that data again, it sees the "Invalid" tag and is forced to fetch the new version from Core A or main memory.
As servers grow to have hundreds of cores (like in large Oracle Exadata or multi-socket systems), "Snooping" becomes too noisy because there are too many messages on the bus.
Snooping: Great for small-to-medium CPUs. Everyone listens to everyone.
Directory-Based: Used in massive high-end servers. A central "Directory" keeps track of who has what. Instead of shouting to the whole group, a core asks the Directory, which then sends a targeted message only to the cores that need to know.
Cache coherency is invisible to the programmer, but it has a massive impact on software performance:
| Scenario | Impact | Result |
| False Sharing | Two cores frequently writing to different variables that happen to be on the same cache line. | The cores "ping-pong" the cache line back and forth, destroying performance. |
| High Contention | Many cores trying to update the same counter (like a database lock). | The bus becomes saturated with "Invalidate" messages, slowing down the system. |
| NUMA Locality | Data moving between caches on different physical sockets. | Higher latency due to the distance the coherency signals must travel. |
Cache coherency is the "glue" that allows multi-core processors to function as a single unit. Without it, parallel computing would be impossible, as every core would be operating in its own isolated, incorrect reality.