Interrupt handling in IBM Power Systems and IBM Z reflects two very different design philosophies:

• Power → general-purpose, OS-driven interrupt model (closer to UNIX/Linux systems)
• Z → hardware-driven, I/O-offloaded, event-based model optimized for massive transaction throughput

Here’s a clear comparison.

1. Core difference (one-line view)

Power: CPU handles interrupts frequently and directly
Z: Hardware minimizes and abstracts interrupts; CPU is involved only when necessary

2. Interrupt model in IBM Power Systems

How it works

On Power:

1. Device completes an operation
2. Sends an interrupt to CPU
3. CPU stops current task
4. OS interrupt handler runs
5. Work is processed
6. CPU resumes previous task

Characteristics

• Traditional interrupt-driven model
• OS (AIX/Linux) manages interrupt routing and handling
• Uses features like:
  • Interrupt coalescing
  • Processor affinity (binding interrupts to cores)

Impact

• More CPU involvement in I/O
• Higher interrupt rates under heavy load
• Needs tuning for:
  • SMP scaling
  • NUMA locality
  • Cache affinity

3. Interrupt model in IBM Z systems

IBM Z uses a fundamentally different approach centered on the channel subsystem.

How it works

1. CPU issues an I/O request
2. Channel subsystem executes I/O independently
3. Multiple operations proceed in parallel
4. CPU is notified only when necessary (completion or exception)

Key concept: Interrupt reduction

Instead of many interrupts:

• Z batches and consolidates notifications
• Uses I/O interruptions only at logical completion points

4. Channel subsystem (game changer)

In IBM Z:

• Dedicated I/O processors handle:
  • Device communication
  • Data transfer
  • Error handling
• CPU is not involved in each I/O step

👉 This drastically reduces interrupt frequency.

5. Types of interruptions in IBM Z

Rather than traditional interrupts, Z uses structured interrupt classes:

• I/O interruptions (completion events)
• External interruptions (timers, signals)
• Machine check interruptions (hardware faults)
• Program interruptions (exceptions)

These are:

• Highly organized
• Efficiently dispatched
• Less frequent but more meaningful

6. Interrupt overhead comparison

7. Effect on I/O-bound workloads

Power:

• Many interrupts during heavy I/O
• CPU cycles consumed in interrupt handling
• Requires tuning (affinity, coalescing)

Z:

• Very few interrupts
• CPU remains free for application logic
• Handles massive transaction volumes efficiently

8. Latency vs throughput trade-off

• Power:
  • Faster immediate interrupt response
  • Better for low-latency device interaction
• Z:
  • Optimized for throughput and scalability
  • Slightly abstracted latency, but far more efficient overall

9. Interaction with virtualization

PowerVM (Power Systems):

• Interrupts are virtualized
• Hypervisor routes interrupts to LPARs
• Can add overhead under heavy load

PR/SM (IBM Z):

• Hardware-assisted partitioning
• Interrupt handling integrated into hardware
• Lower virtualization overhead

10. Simple analogy

IBM Power:

Like a manager being notified every time a task step completes
→ frequent interruptions

IBM Z:

Like a manager being notified only when the entire job is done or if something goes wrong
→ fewer, more meaningful interruptions

11. Key takeaway

IBM Power uses a traditional, OS-driven interrupt model with frequent CPU involvement, while IBM Z minimizes interrupts through its channel subsystem, offloading I/O processing to hardware and notifying the CPU only at key completion points—resulting in far higher efficiency for large-scale I/O workloads.