How does PR/SM implement logical partitions in IBM Z?

How does PR/SM implement logical partitions in IBM Z?

PR/SM (Processor Resource/System Manager) is the firmware hypervisor built into IBM Z that implements Logical Partitions (LPARs) directly in hardware-assisted microcode. Unlike typical software hypervisors, PR/SM is tightly integrated with the processor, memory, and I/O subsystemsβ€”giving it very low overhead and extremely strong isolation.

Here’s how it works architecturally:


πŸ”· 1. What PR/SM Really Is

PR/SM is:

  • A Type-1 hypervisor implemented in firmware/microcode
  • Runs below any operating system
  • Certified at very high security levels (e.g., EAL5+)

πŸ‘‰ It creates multiple independent virtual machines (LPARs) on one physical IBM Z system.


πŸ”· 2. LPAR Abstraction Model

Each LPAR appears as a complete physical machine:

  • Own CPUs (logical processors)
  • Own memory
  • Own I/O devices

πŸ‘‰ OS (like z/OS, Linux, z/VM) runs unchanged, as if on bare metal.


πŸ”· 3. CPU Virtualization (Logical Processors)

πŸ”Ή Physical vs Logical CPUs

  • Physical cores are divided into logical processors
  • Each LPAR gets assigned:
    • Dedicated CPUs OR
    • Shared CPUs

πŸ”Ή Dispatching

PR/SM schedules logical processors onto physical cores:

  • Uses time-slicing for shared CPUs
  • Ensures fairness and priority handling

πŸ‘‰ Overhead is extremely low because:

  • Scheduling is done in firmware (not software)

πŸ”· 4. Memory Virtualization

πŸ”Ή Real Memory Allocation

  • Physical memory is divided into regions per LPAR

πŸ”Ή Address Translation

  • Each LPAR has its own:
    • Virtual β†’ real memory mapping

πŸ”Ή Dynamic Changes

  • Memory can be added/removed using DLPAR (Dynamic LPAR)

πŸ‘‰ Isolation is hardware-enforcedβ€”no LPAR can access another’s memory.


πŸ”· 5. I/O Virtualization (Channel Subsystem Integration)

This is where IBM Z is unique.

πŸ”Ή Channel Subsystem Awareness

PR/SM works with the channel subsystem to virtualize I/O:

  • Devices are assigned to LPARs via:
    • Subchannels
    • Channel paths

πŸ”Ή Direct I/O Access

  • LPARs can access devices almost directly
  • No heavy hypervisor emulation layer

πŸ‘‰ Result:

  • Near-native I/O performance
  • Minimal CPU overhead

πŸ”· 6. Resource Allocation Types

πŸ”Ή Dedicated Resources

  • CPU, memory, I/O fully assigned to one LPAR

πŸ”Ή Shared Resources

  • CPU pools shared across LPARs
  • Managed dynamically

πŸ‘‰ Provides flexibility + efficiency


πŸ”· 7. Hardware-Enforced Isolation

PR/SM ensures strict isolation using:

  • Memory protection keys
  • Address space separation
  • Channel access control

πŸ‘‰ Prevents:

  • Data leakage
  • Unauthorized access

πŸ”· 8. Weight-Based Resource Management

Each LPAR is assigned a weight:

  • Determines CPU share in contention
  • Higher weight = more CPU time

πŸ‘‰ Enables:

  • Workload prioritization
  • Service-level management

πŸ”· 9. Interrupt and Timing Isolation

  • Each LPAR gets virtualized interrupts
  • PR/SM ensures:
    • One LPAR cannot flood another with interrupts
    • Fair interrupt handling

πŸ”· 10. Integration with Higher-Level Hypervisors

PR/SM can host:

  • z/VM
  • Linux on Z
  • z/OS

πŸ‘‰ This enables:

  • Nested virtualization
  • Thousands of virtual machines inside LPARs

πŸ”· 11. Security & Compliance

PR/SM provides:

  • Strong tenant isolation
  • Secure boot integration
  • Compliance for banking/government

πŸ‘‰ One reason IBM Z is used for:

  • Financial systems
  • Government workloads

πŸ”· πŸ”₯ Simple Architecture View

β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”
β”‚ PR/SM β”‚
β”œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”¬β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”¬β”€β”€β”€β”€β”€β”€β”€β”€
β”‚ LPAR 1 β”‚ LPAR 2 β”‚ LPAR 3β”‚
β”‚ (z/OS) β”‚ (Linux) β”‚ (z/VM)β”‚
β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”΄β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”΄β”€β”€β”€β”€β”€β”€β”€β”˜
β”‚ β”‚ β”‚
CPU / Memory / I/O (Virtualized)

πŸ”· πŸ”₯ Why PR/SM Is Different from x86 Hypervisors

FeaturePR/SM (IBM Z)x86 Hypervisors
ImplementationFirmwareSoftware
OverheadExtremely lowHigher
I/O virtualizationHardware-integratedSoftware-driven
SecurityHardware enforcedSoftware + hardware
ScalabilityMassive (LPARs + VMs)Moderate

πŸ”· πŸš€ Bottom Line

PR/SM implements LPARs by:

βœ” Virtualizing CPU, memory, and I/O in firmware
βœ” Integrating deeply with hardware (especially I/O channels)
βœ” Enforcing strict isolation at hardware level
βœ” Providing dynamic resource allocation
βœ” Delivering near-native performance with minimal overhead

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