What is cache coherency protocol (MESI/MOESI)?
In a multi-core world, your CPU is like a team of researchers sharing a single whiteboard (Main Memory). Each researcher has their own notebook (L1/L2 Cache). If one researcher changes a formula in their notebook but doesn't tell the others, the whole project falls apart.
Cache Coherency Protocols are the "communication rules" that ensure every core sees the same data at the same time. MESI is the classic standard, while MOESI is the high-performance evolution used by AMD and ARM.
MESI is an acronym for the four states a cache line can be in. It uses a "Snooping" mechanism where every core "listens" to a shared bus to see what other cores are doing.
M (Modified): You have the only copy of the data, and you’ve changed it. It is now different from Main Memory. You are responsible for writing it back later.
E (Exclusive): You have the only copy, but it matches Main Memory. You can change it to Modified whenever you want without asking permission.
S (Shared): Multiple cores have a copy of this data. If you want to change it, you must send an "Invalidate" signal to everyone else first.
I (Invalid): Your notebook entry is garbage. Someone else changed the "whiteboard," and your copy is out of date. You must fetch it again.
MOESI (used in AMD EPYC and Ampere chips on OCI) adds a fifth state: O (Owned). This state solves a massive bottleneck in the MESI model.
In MESI, if Core A has Modified data and Core B wants to read it, Core A must write that data back to the slow Main Memory (RAM) first so Core B can read it. This is like stopping a meeting to go to the printer.
In MOESI, Core A can move the data to the Owned state.
Owner (O): Core A keeps the modified data and gives a copy to Core B (who marks it as Shared).
No RAM Trip: The data is shared cache-to-cache without touching the slow Main Memory. Core A remains the "Owner" and is eventually responsible for updating the RAM, but the cores can keep working at full speed in the meantime.
In a cloud environment like OCI, where you might have 128 cores on a single Ampere A1 instance, cache coherency is the difference between a fast app and a "stuttering" one.
Scalability: As you add more cores, the "Snooping" traffic (cores shouting "I'm changing this!") can overwhelm the CPU. MOESI reduces this traffic by allowing cores to share "dirty" (modified) data directly.
Database Performance: Databases rely on "Spinlocks" (cores waiting for a tiny bit of data to change). MOESI allows these locks to be passed between cores almost instantly.
Context Switching: When a virtual machine moves from one physical core to another, these protocols ensure the new core quickly "vows" the data from the old core's cache.
| Feature | MESI (Intel Style) | MOESI (AMD/ARM Style) |
| States | 4 (M, E, S, I) | 5 (M, O, E, S, I) |
| Shared Dirty Data | Not allowed; must write to RAM. | Allowed via "Owned" state. |
| RAM Latency | Higher during core-to-core sharing. | Lower (Cache-to-Cache is 10x faster). |
| Bus Traffic | High (frequent write-backs). | Lower (fewer write-backs). |
"MESI ensures your cores don't lie to each other, but MOESI ensures they don't slow each other down. By adding the 'Owned' state, modern CPUs turn a congested traffic jam of memory writes into a high-speed express lane of cache-to-cache sharing."