What is cache hierarchy in modern Oracle-supported CPUs?
In 2026, the battle for cloud performance has moved from raw clock speeds to cache efficiency. As CPUs add more cores, the bottleneck shifts to how quickly those cores can access data.
Oracle Cloud Infrastructure (OCI) supports three primary CPU architectures—Intel Xeon, AMD EPYC, and Ampere (Arm)—each with a unique "storage room" (cache) design. Here is the breakdown of the modern cache hierarchy for your blog.
Intel’s modern "Sapphire Rapids" and "Emerald Rapids" architectures (used in OCI’s Optimized and Standard shapes) use a balanced, mesh-based hierarchy.
L1 Cache (Private): 80 KB per core (48 KB Data + 32 KB Instruction). This is the "fast-twitch" memory for immediate execution.
L2 Cache (Private): 2 MB per core. Intel significantly increased this in recent generations to reduce "misses" that force the CPU to go to the slower L3 cache.
L3 Cache (Shared/Non-Inclusive): Roughly 1.875 MB to 5 MB per core (depending on the specific SKU). It uses a "non-inclusive" design, meaning it doesn't have to mirror the L2 data, allowing for more unique data to be stored across the chip.
AMD’s "Zen 4" and "Zen 5" architectures (found in OCI’s E5 and E6 shapes) use a "Chiplet" (CCD) design that focuses on massive L3 density.
L1 Cache (Private): 64 KB per core.
L2 Cache (Private): 1 MB per core. While smaller than Intel’s L2, AMD offsets this with a much faster path to the L3.
L3 Cache (Shared per CCD): 32 MB shared across 8 cores. In the E6 "Turin" shapes, this distributed cache is massive. Because 8 cores share one large 32 MB bucket, multi-threaded applications (like databases) can share data between cores without ever leaving the silicon.
Ampere is the "Cloud Native" choice in OCI (Standard A1 and A4 shapes). Its hierarchy is built for linear scalability—meaning performance doesn't drop as you add more users to a server.
L1 Cache (Private): 64 KB I-cache and 64 KB D-cache per core.
L2 Cache (Private): 1 MB to 2 MB per core (depending on the generation). Crucially, this cache is truly private—neighboring cores cannot "evict" your data, which eliminates the Noisy Neighbor effect at the CPU level.
System Level Cache (SLC): Instead of a traditional L3, Ampere uses a large Distributed SLC (up to 64MB+) that acts as a high-speed buffer between the cores and the DDR5 memory.
| Feature | Intel (Optimized) | AMD (Standard E6) | Ampere (A4 Arm) |
| L2 Size | 2 MB (Largest) | 1 MB | 2 MB |
| L3 Design | Mesh Interconnect | CCD Shared (High Density) | Distributed SLC |
| Best For | Single-thread speed | Databases / Parallelism | Cloud-native / Web Scale |
| Key Advantage | Lowest L2 latency | Massive shared data pool | Deterministic performance |
"If you're running a Java application, Intel’s large L2 cache is your best friend. If you’re running a Relational Database, AMD’s shared L3 chiplet design will significantly speed up cross-thread communication. And if you're building Microservices, Ampere’s isolated L2 ensures one container doesn't slow down another."