The Coherent Accelerator Processor Interface (CAPI) is an architecture developed by IBM to let external accelerators (FPGAs, ASICs, GPUs) attach to a POWER system as if they were coherent peers of the CPU, not just peripheral devices.

On systems like IBM POWER10 (and earlier POWER8/9), CAPI fundamentally changes how accelerators interact with memory and software.

🧠 Core idea of CAPI

❌ Traditional model (PCIe): accelerator = I/O device
✅ CAPI model: accelerator = coherent processor sharing memory

This eliminates much of the overhead of:

• DMA setup
• Data copies
• OS intervention

🏗️ CAPI Architecture Components

1. ⚡ Physical layer: PCIe-based transport

CAPI uses:

• PCI Express as the physical link
• Standard slots and signaling

👉 But adds a custom protocol layer on top

2. 🧩 Coherent Accelerator Processor Proxy (CAPP)

This is the key hardware block in the CPU:

• Sits between:
  • CPU cache hierarchy
  • PCIe interface

Functions:

• Maintains cache coherence between CPU and accelerator
• Translates accelerator requests into CPU memory operations
• Tracks memory consistency

👉 Makes accelerator appear like another coherent agent

3. 🔄 Coherent memory model

With CAPI:

• Accelerator can:
  • Directly read/write system memory
  • Access virtual addresses (not just physical)
• Shares the same address space as CPU

👉 No need for:

• Explicit DMA buffers
• Address translation in software

4. 📂 Shared page tables

CAPI integrates with system MMU:

• Accelerators use same page tables as CPU
• Hardware handles:
  • Address translation
  • Protection checks

👉 Enables:

• Simplified programming model
• Secure access control

5. ⚙️ Accelerator functional unit (AFU)

On the accelerator side:

• Logic is implemented as an AFU (Accelerator Functional Unit)

AFU:

• Issues memory requests
• Participates in coherence protocol
• Appears like a compute unit attached to CPU fabric

🔐 6. Coherence protocol integration

CAPI ties into POWER cache coherence:

• Ensures:
  • Data consistency between CPU caches and accelerator
• Handles:
  • Cache line states
  • Invalidations and updates

👉 Eliminates stale data issues

🚀 7. Interrupt and synchronization model

• Low-latency communication between CPU and accelerator
• Lightweight signaling (doorbells, queues)

👉 Faster than traditional device interrupts

⚡ How CAPI differs from traditional PCIe

🧩 Evolution: OpenCAPI

CAPI evolved into:

• OpenCAPI

Enhancements:

• Higher bandwidth than PCIe
• Independent physical layer
• Broader ecosystem support

📊 Why CAPI matters for performance

✔ Eliminates data copies

• No CPU-mediated DMA transfers
• Direct shared-memory access

✔ Reduces latency

• Coherent access avoids round trips

✔ Improves programmability

• Accelerator behaves like a thread/process

✔ Enables fine-grained acceleration

• Not just bulk offload, but tight CPU-accelerator coupling

🧠 Big insight

CAPI transforms accelerators from:

❌ “external devices that you send data to”
into
✅ “coherent compute units that operate directly on your memory”

🔥 Real-world impact

• FPGA acceleration for databases
• Compression/encryption offload
• AI inference pipelines
• High-frequency trading systems